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Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade
http://hdl.handle.net/10445/5726
http://hdl.handle.net/10445/57261864cdf5-1cbf-42c3-9705-abab70e9fa05
名前 / ファイル | ライセンス | アクション |
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2011-03-01 | |||||
タイトル | ||||||
タイトル | Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Akita, Junichi
× Akita, Junichi× Takagi, Hiroaki× Doumae, Keisuke× Kitagawa, Akio× 戸田, 真志× Nagasaki, Takeshi× 川嶋, 稔夫 |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed. | |||||
書誌情報 |
IEICE Trans. on Electronics 巻 E90-C, 号 10, p. 1869-1875, 発行日 2007-10-01 |
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査読有無 | ||||||
値 | あり/yes | |||||
研究業績種別 | ||||||
値 | 原著論文/Original Paper | |||||
単著共著 | ||||||
値 | 共著/joint | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | https://doi.org/10.1093/ietele/e90-c.10.1869 | |||||
権利 | ||||||
権利情報 | copyright©2007 IEICE | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
出版者 | ||||||
出版者 | 電子情報通信学会 |